My notes suggest this was an interview question at one time. What I didn’t note is when, who, and whether I gave it or received it. The date stamp suggests late 1990s/early 2000s.
State assumptions and determine the voltage at the output.
Assumption: Neither transistor is saturated. Base current is zero.
Voltage at NPN base is (20/40)*12 = 6V (with current equal to 12/40k = 0.3mA)
Since not in saturation, assume both VBE = 0.6V. Voltage at emitter of NPN is 5.4V
Current through R5 is 5.4/1k = 5.4mA
Voltage at collector of NPN is 11.4V [VCE,N = (11.4 – 5.4) = 6V ; not saturation assumption valid]
Current through R3 is 0.6/20k = 30 uA
Current through R4 is (5.4mA – 30 uA) ~ 5.4mA. Voltage across R4 is close to 5.4V
Therefore, voltage at output is (5.4 + 5.4) = 10.8V [VCE,P = (12 – 10.8) = 1.2V ; not saturation assumption valid]