PLL – Basic Design – Dave McGlone

Introduction

A phase-locked loop was designed and laid out on the AMIS (now ONSemi) C5 process. This is a 0.5um process having 3M with a poly-poly cap and a high-R poly resistor.

General Design Considerations

It is usually desirable to run the VCO at higher frequencies then use output dividers to get desired output frequency. While this results in lower jitter the higher switching rates consume more power. Conversely, a lower VCO frequency consumes less power but with higher jitter.

The use of a charge pump allows infinite pull-in range and zero steady-state error as long as the frequency remains within the range of the VCO – the closed loop will always attempt lock. The degree of correction achieved is proportional to phase difference between reference frequency and PLL out.

Basic Operation

The feedback loop will synchronize the phase (and frequency) of the oscillator to some reference signal.

The basic structure consists of phase/frequency detector (PFD) and charge pump (CP) forming a phase detector; a filter which defines the dynamic characteristics of the loop; and a voltage-controlled oscillator (VCO) which provides the desired output signal. This basic structure is often enhanced with some form of frequency scaling – the simplest being flip-flops configured as binary frequency dividers.

In lock, the VCO output is the same or some controlled multiple of a frequency division factor. The phase difference between the output and reference signals is a constant – often desired to be zero.

Terminology

Lock/Capture Range:   The frequency range in which the PLL can operate.
Pull-In Range:              Frequency range where PLL will always lock.
Pull-Out Range:             Frequency range of stability. If lock is lost within this range, lock will be re-captured.
Hold Range:                 Range where phase tracking is maintained.

Basic PLL System

When in-lock, the PLL can be modeled as a linear system:

As with any linear system, the transfer function of this feedback system can be expressed as:

$\begin{displaymath}T(s) \; = \; \frac{G(s)}{\, 1 \, + \, G(s) \, H(s) \, } \quad \Rightarrow \quad Out(s) \; = \; In(s) \, T(s)\end{displaymath}$

where:

$\begin{displaymath}G(s) \; = \; K_d \, F(s) \, \frac{ \, K_v \, }{s} \; \; \text{and} \; \; H(s) \; = \; \frac{1}{\, N \, }\end{displaymath}$

For input stimulus phase $\theta_i$ :

$\begin{displaymath}\theta_e(s) \; = \; \theta_i(s) \, \frac{1}{\, 1 \, + \, G(s) \, H(s) \, } \; \; = \; \; \frac{N \, s }{\, K_d \, F(s) \, K_v \, + \, N \, s \, }\end{displaymath}$

$\begin{displaymath}\begin{align}\theta_o(s) \; = \; &\theta_i(s) \, \frac{G(s)}{\, 1 \, + \, G(s) \, H(s) \, } \\\\\Rightarrow \; &\theta_i(s) \, \frac{K_d \, F(s) \, K_v/s}{\, 1 \, + \, \left\{ \, \left[ \, K_d \, F(s) \, K_v/s \, \right] / N \, \right\} \, } \; \; = \; \; \theta_i(s) \, \frac{K_d \, F(s) \, K_v \, N}{\, K_d \, F(s) \, K_v \, + \, N \, s \, }\end{align}\end{displaymath}$

Since Kd and Kv are fixed gain functions and only add a single pole related to the VCO, the filter is used to control the dynamic operation of the PLL. This example will use a somewhat more complex implementation of the filter function.

PLL System Components

XOR Phase-Frequency Detector (PFD)

A simple manifestation of a phase detector is a basic XOR gate. The truth table for XOR is:

$XOR = \begin{array}{cc|c}A & B & Y \\\hline0 & 0 & 0 \\0 & 1 & 1 \\1 & 0 & 1 \\1 & 1 & 0 \\\end{array} \right.$

It can be seen that a pulse whose width is equal to the difference between the reference and feedback pulse is generated but does not indicate which pulse leads.

When used as a phase detector, this network produces an output stream of pulses proportional to the difference between the phase and frequency of two inputs. The output voltage is proportional to the phase difference of the two signals. This output is quasi-static; it is periodic to 2π radians.

If there is no phase difference, a free-running voltage occurs whose value is network dependent – often at or near the supply voltage mid-point. The following illustration demonstrates the condition of open-loop with no stimulus.

Although not necessary, it is usually desirable for the nominal operation to be close to the desired lock condition; i.e., the free-running frequency of the VCO is near the desired operating frequency and the control voltage at about the mid-point of the control range.

Recall that in locked operation, the phase difference will be constant – ideally zero.

The phase error is expressed as:

$\begin{displaymath}\theta_e \; = \; \theta_i \, - \, \theta_o\end{displaymath}$

When locked, the VCO operates at a frequency which is matched in phase with the input signal and the phase error remains constant (often zero)

The phase detector has a constant gain $K_d$ expressed as:

$\begin{displaymath}K_d \; = \; \frac{\, dv_d \,}{d\theta_e} \; \; = \; \; \frac{v_{d,hi} \, - \, v_{d,lo}}{\, \theta_{e,max} \, - \theta_{e,min} \, } \; \; = \; \; \frac{ \, 1 \, - \, ( \, -1 \, ) \, }{\pi \, - \, 0} \; \; = \; \; \frac{\, 2 \,}{\pi}\end{displaymath}$

From this, the VCO control voltage for some value of phase error $\theta_e$ is:

$\begin{displaymath}V_d \; = \; K_d \, \theta_e \, + \, v_{d0}\end{displaymath}$

where $v_{d0}$ is the free-running phase detector output voltage.

The error signal $e$ – a measure of the phase difference between the reference and feedback signals – is a sequence of pulses which need to be averaged by filtering. The average value of $e$ is found to be:

$\begin{displaymath}e_{avg} \; = \; -1 \, + \, 2 \, \frac{W}{\, T/2 \, } \; = \; \frac{\, 4 \, W \, }{T} \, - \, 1\end{displaymath}$

A suitable system representation of the phase detector is:

Tri-State Phase-Frequency Detector

A better topology of a PFD is shown below. This version is constructed from two DFFs and a NAND gate and has a three-state output. The PFD generates pulses of a type that differentiate between the leading edge of the input or reference phases. If the rising edge of f1 leads the rising edge of f2, an UP pulse is asserted. The UP signal stays H until the rising edge of f 2 occurs and resets the DFFs.

If the rising edge of $f_2$ leads the rising edge of $f_1$ , a $\text{DOWN}$ pulse is now asserted. The $\text{DOWN}$ signal stays H until the rising edge of $f_1$ occurs. If the two inputs are equal in phase, both outputs stay L.

This topology is popular as it is a simple design and has a range of 4π instead of π as in the 2-state or in multiplying topologies (even as an analog designer, this discussion doesn’t go there).

The waveforms for this structure are shown:

The response of this system is:

This phase detector has a gain $K_d$ of:

$\begin{displaymath}K_d \; = \; \mathrm{d}v_d/\mathrm{d}\theta_e \; = \; \frac{v_{d,hi} \, - \, v_{d,lo}}{\,\theta_{e,max} \, - \, \theta_{e,min} \, } \; = \; \frac{ 1 \, - \, (-1)}{\, 2 \, \pi \, - \, (-2 \, \pi) \, } \; = \; \frac{2}{4 \, \pi} \; = \; \frac{1}{\, 2 \, \pi \, }\end{displaymath}$

and a system representation of:

Filter

The phase detector output is actually a stream of pulses representing the phase difference between the input and reference signals. A low-pass filter is used to average this voltage for controlling the VCO. The filter represents a compromise between the wide bandwidth necessary for tracking phase errors within a large frequency range and the need to minimize noise attenuation which requires a small pass-band. This noise appears as jitter in the output frequency. Jitter reduction requires a reduction in filter bandwidth.

The PLL system order is one greater than the order of the filter. A 1st-order PLL is one in which a simple attenuator is used in place of the filter. The 1^st-order PLL will track phase error at a reduced frequency range. Using a 1^st-order LP filter converges to zero-error in phase but non-zero in frequency. A 3^rd-order PLL – one with a 2^nd-order filter – is required to track frequency offsets.

An active filter improves PLL performance at a cost of power, active bandwidth, and complication. Passive filters are easier to implement at lower cost and therefore more commonly utilized. This implementation will incorporate a lead-lag filter with a charge-pump integrator.

Voltage-Controlled Oscillator (VCO)

The basic VCO assumes a linear relationship between the control voltage and output frequency over some defined range. Operation outside this range is beyond the scope of this discussion.

Under the assumption of linear operation, the gain is constant and has a slope $K_v$ which is expressed as:

$\begin{displaymath}K_v \; = \; \mathrm{d}\omega_o/\mathrm{d}v_c \; = \; \frac{\, \omega_2 \, - \, \omega_1 \,}{\,v_2 \, - \, v_1 \, } \; \; Hz/V\end{displaymath}$

Define the control voltage for lock as vco. The frequency deviation due to a change in control voltage is expressed as:

$\begin{displaymath}\Delta \omega_o \; = \; K_v \, ( \, v_c \, - \, vco \, )\end{displaymath}$

Common topology families for VCOs are LC and ring oscillators. Another possibility is a relaxation oscillator which has a frequency controlled by the rate of charge and discharge of a capacitor (an inductor could be used but generates a magnetic field – potential EMI – instead of the electric field of a capacitor). The frequency is changed by controlling the charge/discharge rate.

Higher frequency applications often use a resonant structure. The frequency of operation is determined by a tuned LC network where a varactor – a voltage-controlled capacitance – is used to control the VCO frequency.

$\begin{displaymath}\omega_o \; = \; \frac{1}{\, \sqrt{ \, L \, C_v \, } \, }\end{displaymath}$

However, for this design, a modified ring oscillator is used. A voltage-controlled current source provides the biasing for a closed loop of many (n = odd) cascoded inverters. The biasing controls the propagation time though the inverters; the use of an odd number of inverters provides the positive feedback necessary for oscillation.

A higher frequency implementation would use an LC tank topology.

Frequency Divider

Although not necessary for basic PLL operation, there are many advantages to the addition of frequency dividers within the PLL topology.

The most common use of a divider is in the feedback loop. This allows the use of low frequency oscillators for a higher frequency output. More complex arrangements of dividers allow the synthesis of “odd” frequencies from a common oscillator.

The relationship between the output frequency of the PLL and the reference (feedback) frequency is:

$\begin{displaymath}f_{PLL} \; = \; N \, \times \, f_{ref}\end{displaymath}$

where N is the division factor. For binary factors, DFF topologies are common.

Example Design

A step-change in frequency from f1 to f2 is applied to the PLL.

Consider the graphical response shown:

The PLL settles to the new frequency in time $t_s$ . During this transition, the response oscillates at the system natural frequency $f_n$ .

The system design equations are as follows:

1) The VCO operates over a frequency range of $f_{lo}$ to $f_{hi}$ MHz. The VCO control factor is:

$\begin{displaymath}K_v \; = \; \mathrm{d}f/\mathrm{d}v\end{displaymath}$

The divide ratio is ¼ which is defined by N = 4.

2) The natural frequency is:

$\begin{displaymath}f_n \; = \; -\frac{1}{\, 2 \, \pi \, t_s \, \delta \, } \; ln\left(\frac{f}{\, f_{step}\right) \, }\end{displaymath}$

3) The loop bandwidth is:

$\begin{displaymath}\omega_{-3dB} \; = \; \pi \, f_n \, \left( \, \delta \, + \, \frac{1}{\, 4 \, \delta \, } \, \right)\end{displaymath}$

4) The capacitor can be selected to be:

$\begin{displaymath}C_2 \; = \; \frac{I \, K_v}{\, N \, ( \, 2 \, \pi \, f_n \, )^2 \, }\end{displaymath}$

and the resistor:

$\begin{displaymath}R_1 \; = \; 2 \, \delta \, \sqrt{ \, \frac{N}{\, I \, K_v \, C_2 \, } \, }\end{displaymath}$

The value of C1 is not critical but should be about 1/10 the value of C2.

The value of ( $R_3 \, C_3$ ) should be about 1/10 of ( $R_2 \, C_2$ ). One way to accomplish this is to set R3 = R1 and C3 = C1.

Phase-Frequency Detector

One manifestation of a PFD is shown below. This version is constructed from two DFFs and a NAND gate. The PFD generates pulses of a type that differentiate between the leading edge of the input or reference phases. If the rising edge of f1 leads the rising edge of f2, an UP pulse is asserted. The UP signal stays H until the rising edge of f 2 occurs and resets the DFFs.

If the rising edge of f 2 leads the rising edge of f 1, a $\text{DOWN}$ pulse is now asserted. The $\text{DOWN}$ signal stays H until the rising edge of f 1 occurs. If the two inputs are equal in phase, both outputs stay L.

This topology is popular as it is a simple design and has a range of 2π instead of π as in the 2-state or multiplying topologies.

Charge Pump

The charge pump converts the $\text{UP}$ and $\text{DOWN}$ pulses of the PFD into a single output of current pulses. These pulses are averaged by the capacitor of the low-pass filter. The charge pump provides “infinite” gain which allows an unbounded pull-in range. In practice, this statement is based on the assumption of linear system operation – the range is limited by the region of system linearity.

The charge pump consists of a constant current source and sink connected to the output by switches controlled by the $\text{UP}$ and $\text{DOWN}$ signals from the PFD. An $\text{UP}$ signal activates the current source; this current charges the filter capacitor. The $\text{DOWN}$ signal activates the current sink which pulls charge from the filter capacitor.

Note that the sink and source currents should be equal.

It is the combination of the PFD and Charge Pump that form the phase detection portion of the system. The combined gain of this stage is found as:

$\begin{displaymath}K_d \; = \; \frac{I}{\, 2 \, \pi \, }\end{displaymath}$

The factor of 2π is due to the phase detector being periodic with a period of 2π.

In the particular topology used, a bias network establishes a reference current of 10 μA. This current is mirrored in such a way as to force the source and sink currents to be equal.

For hand design purposes, I = 10 μA.

The phase detector/charge pump is susceptible to errors such as:

1. Mismatch in source/sink currents will cause asymmetrical timing in the pulses applied to the filter. This will manifest itself as mismatch in the VCO control voltage during the capture sequence (the error is minimal during LOCK).

2. Leakage current through the switches will create variations in the VCO control voltage during LOCK.

3. Timing mismatches in the PFD will create errors in pulse widths causing an incorrect voltage to be applied to the VCO.

Loop Filter

In this example topology, a passive filter is appropriate for use with the charge pump. A passive filter is easier to implement, uses no power, and adds less noise than an active circuit (thermal noise of the resistors) A 3rd-order example is presented (which makes the PLL a 4th-order system)

The transfer function of this filter is:

$\begin{displaymath}F(s) \; = \; \frac{(\, 1 \, + \, s \, R_1 \, C_2 \, ) \, ( \, C_1 \, + \, C_2 \, + \, C_3 \,)}{\, s \, C_1 \, ( \, C_1 \, + \, C_2 \, + \, C_3 \, + \, s \, R_1 \, C_1 \, C_2 \, ) \, ( \, 1 \, + \, s \, R_2 \, C_3 \, ) \, }\end{displaymath}$

In terms of time constants:

$\begin{displaymath}F(s) \; = \; \frac{1 \, s \, T_2}{\, s \, C_1 \, ( \, 1 \, + \, s \, T_1 \,) \, ( \, 1 \, + \, s \, T_3 \,) \, } \; = \; \frac{1}{\, s \, C_1 \, } \, \frac{1 \, s \, T_2}{ \, ( \, 1 \, + \, s \, T_1 \,) \, ( \, 1 \, + \, s \, T_3 \,) \, }\end{displaymath}$

where:

$\begin{displaymath}T_1 \; = \; \frac{R_1 \, C_1 \, C_2}{\, C_1 \, + \, C_2 \, + \, C_3 \, } \qquad T_2 \; = \; R_1 \, C_2 \qquad T_3 \; = \; R_2 \, C_3\end{displaymath}$

VCO

The preferred VCO topology for phase noise performance is a resonant LC tank network. A common oscillator type is the Colpitts, but in practice the Colpitts requires a much larger device area than a cross-coupled tank.

A modified differential-pair topology is illustrated.

The voltage between the terminals is caused by the bias current through the parasitic resistance of the tank. Frequency control is via the voltage controlled capacitor (varactor) and the bias current. The capacitances of the MOSFETs need to be considered in the design effort.

The conductance of the inductor is expressed:

$\begin{displaymath}g_L \; = \; \frac{1}{R_p} \, + \, \frac{R_s}{\, \omega^2 \, L_s^2 \, } \; = \; \frac{1}{R_p} \, + \, \frac{1}{\, Q_L^2 \, R_s \, }\end{displaymath}$

where QL = ω LS / RS

The conductance of the varactor can be expressed:

$\begin{displaymath}g_v \; = \; \omega^2 \, C_v^2 \, R_v \; = \; \frac{1}{\, Q_v^2 \, R_v \, }\end{displaymath}$

where $Q_v \, = \, ( \, \omega \, C_v \, R_v \, )^{-1}$

The total inductance of the circuit is found to be $L_{tank} \, = \, 2 \, L$ .

The total capacitance of the tank is found to be:

$\begin{displaymath}C_{tank} \; = \; ½ \, ( \, C_N \, + \, C_P \, + \, C_v \, + \, C_L \, + \, C_{load} \, )\end{displaymath}$

And the total conductance of the tank is:

$\begin{displaymath}g_{tank} \; = \; ½ \, ( g_{oN} \, + \, g_{oP} \, + \, g_v \, + \, g_L \, )\end{displaymath}$

The oscillation frequency range is determined by the limits of the varactor capacitance:

$\begin{displaymath}\omega \; = \; \frac{1}{ \, \sqrt{ \, L_{tank} \, C_{tank} \, } \, }\end{displaymath}$

The loop gain needs to be such that ½ $( \, g_{mn} \, + \, g_{mp} \, ) \, \geq \, 3 \, g_{tank,max}$ .

The factor 3 is somewhat arbitrary but should be sufficiently greater than 1 to set the gain to a level sufficient that oscillations begin.

Unfortunately, a higher-level criteria for selecting the VCO topology is the process used. If the process does not allow inductors and/or varactors, a ring oscillator is the preferred topology. If the performance of the varactor LC tank is necessary, an appropriate process is necessary. (Although it should be noted that spiral inductors can usually be implemented for values on the order of nH for higher frequencies.

A ring oscillator is constructed of an odd number of inverters tied together in a “ring”. The frequency of oscillation is defined by the number of stages, the input/output capacitance of each stage, and the amount of current available for charging/discharging this capacitance. This structure can be voltage-controlled by adjusting the charge/discharge current.

One method of doing this is by controlling the inverter supply current with a topology similar to that shown below (higher levels of performance can be obtained with a more complex structure).

The bias voltages are generated by a structure whose current can be controlled by a single resistance. This value is generally set according to the requirements of the system and may or may not be adjustable after manufacturing.

Frequency Divider

The frequency limits of the divider network define the range of frequency synthesis available in the system. A simple binary divider can be constructed of DFFs configured as a divide-by-2 network – with the restriction that divide values be powers-of-2…not always desirable.

Jitter

Jitter is the short term variation in pulse position about the desired location: the period, phase, duty cycle and/or other timing characteristics vary from the ideal.

Among the common causes of jitter are internal thermal and flicker noise, variations in input source frequency, unbalanced charge pump currents, and other similar factors – primarily affecting the VCO control voltage.

Noise Analysis

System noise can be predicted by incorporating and characterizing the various noise sources into the system diagram. Incorporating the block expansions of above, the noiseless system appears as

Adding the system-level noise sources…

$\mathrm{n_{JIN}}$       jitter present on the input signal
$\mathrm{n_{FT}}$         feed-through of the input signal through the phase detector
$\mathrm{n_{CP}}$        noise created within the charge pump
$\mathrm{n_{FIL}}$      created by the filter. Although this modulates the VCO voltage, it is usually small
$\mathrm{n_{VCO}}$    VCO noise: it has a -20 dB/dec roll-off
$\mathrm{n_{div}}$       jitter present from the divider

The model can be simplified by combing all noise sources except the VCO into one representation referred to the PD output; the VCO noise is left as is. (All noise sources except VCO are assumed Gaussian)

System Transfer Functions

The open-loop response of this system is:

$\begin{displaymath}A(f) \; = \; \frac{1}{\, 2 \, \pi \,} \, I_{CP} \, F(f) \, \frac{K_v}{\, \jmath \, f \, } \, \frac{1}{N}\end{displaymath}$

with the closed-loop response being defined as:

$\begin{displaymath}G(f) \; = \; \frac{A(f)}{\, 1 \, + \, A(f) \, } \; = \; \left( \, 1 \, + \, \jmath \, \frac{2 \, \pi \, f \, N}{\, F(f) \, I_{CP} \, K_v \, } \, \right)^{-1}\end{displaymath}$

The system output with respect to the phase-detector output noise is:

$\begin{displaymath}\begin{align}\frac{\Theta_{out}(f)}{\, n_{PD}(f) \, } \; &= \; \frac{I_{CP} \, F(f) \, \frac{K_v}{\, \jmath \, f \,}}{\, 1 \, + \, \frac{1}{2 \, \pi} \, I_{CP} \, F(f) \, \frac{K_v}{\, \jmath \, f \, } \, \frac{1}{N} \, } \\\\&= \; 2 \, \pi \, N \, \frac{\frac{1}{2 \, \pi} \, I_{CP} \, F(f) \, \frac{K_v}{\, \jmath \, f \, } \frac{1}{N}}{\, 1 \, + \, \frac{1}{2 \, \pi} \, I_{CP} \, F(f) \, \frac{K_v}{\, \jmath \, f \, } \frac{1}{N} \, } \\\\&= \; 2 \, \pi \, N \, \frac{A(f)}{\, 1 \, + \, A(f) \, } \; \; = \; \; 2 \, \pi \, N \, G(f)\end{align}\end{displaymath}$

(Noise is characterized as a function of frequency “f” in Hz rather than radians where s = $\jmath \, \omega \, \Rightarrow \, \jmath \, 2 \, \pi \, f )$

The system output with respect to the VCO output noise is:

$\begin{displaymath}\frac{\Theta_{out}(f)}{\, n_{vco}(f) \, } \; = \; \frac{1}{\, 1 \, + \, \frac{1}{2\, \pi} \, I_{CP} \, F(f) \, \frac{K_v}{\, \jmath \, f \, } \frac{1}{N} \, } \;\; = \; \; 1 \, - \, G(f)\end{displaymath}$

Charge Pump Noise

The charge pump noise is referred back to the PFD output by a simple scaling of:

$\begin{displaymath}\frac{\Theta_{out}(f)}{\, n_{CP}(f) \, } \; = \; \frac{1}{\, I_{CP} \, } \, \frac{\Theta_{out}(f)}{\, n_{PD}(f) \, } \; = \; \frac{1}{\, I_{CP} \, } \, 2 \, \pi \, N \, G(f)\end{displaymath}$

It follows that the charge-pump contribution to the output noise is:

$\begin{displaymath}S_{\Phi,out}(f)\vbar_{CP} \; = \; \left(\frac{1}{I_{CP}}\right}^2 \, ( \, 2 \, \pi \, N \, )^2 \, S_{nCP}(f)\end{displaymath}$

Larger $I_{CP}$ decreases noise; larger $N$ increases noise.

Loop Filter

The output of the charge pump expects to see a capacitive load in order to implement an integrator. The filter structure used with this forms a lead-lag load to the charge pump. (making this PLL a 3rd-order network)

This structure has a transfer function of:

$\begin{displaymath}F(s) \; = \; \frac{1}{\, s \, C_t \, } \, \frac{1 \, + \, s \, R \, C_2 \, }{1 \, + \, s \, R \, C_{||} \, } \; = \; \frac{1}{\, s \, C_t \, } \, \frac{1 \, + \, s /\omega_z \, }{1 \, + \, s /\omega_p \, }\end{displaymath}$

where:

$\begin{displaymath}C_t \; = \; C_1 \, + \, C_2 \qquad C_{||} \; = \; \frac{C_1\, C_2}{ \, C_1 \, + \, C_2 \, }\end{displaymath}$

In the frequency domain:

$\begin{displaymath}F(f) \; = \; \frac{1}{\, \jmath \, 2 \, \pi \, f \, C\, } \, \frac{1 \, + \, \jmath \, \left( \, f/f_z \, \right) \, }{1 \, + \, \jmath \, \left( \, f/f_p \, \right) \, }\end{displaymath}$

Aside from the ease of integration, an advantage of this structure comes from the integrator in F(s) which forces a steady-state phase error of zero as well as minimizing jitter. However, there is an undesired pole/zero pair which causes a degree of peaking in the loop response. Peaking is minimized with lower-value zero … which requires a large capacitor.

Consider this closed-loop system:

$\begin{displaymath}T(s) \; = \; \frac{\frac{A_N}{A_D}}{\, 1 \, + \, \frac{A_N}{A_D} \, \frac{B_N}{B_D} \, } \; = \; \frac{A_N \, B_N}{\, A_D \, B_D \, + \, A_N \, B_N \, }\end{displaymath}$

Zeroes in the feedback loop are not zeroes in the closed loop function.

Jitter Noise

Assume jitter has a Gaussian distribution. Assuming discrete time signals, the spectra can be calculated as:

$\begin{displaymath}S_{\Phi ,jit} \, \mathbb{e}^{\jmath \, 2 \, \pi \, f \, T} \; = \; \left|\frac{\, 2 \, \pi \, }{T} \right|^2 \, \left[ \, S_{\Delta T,jit} \, \mathbb{e}^{\jmath \, 2 \, \pi \, f \, T}\, \right]^2\end{displaymath}$

VCO Noise

The noise of a VCO can be represented as shown in the following:

The noise appears as time-domain phase jitter in the output signal:

$\begin{displaymath}\text{out}(t) \; = \; 2 \, cos[ \, 2 \, \pi \, f_o \, t \, + \, \Phi_{out}(t) \, ]\end{displaymath}$

This may be expanded to:

$\begin{displaymath}\text{out}(t) \; = \; 2 \, cos[ \, 2 \, \pi \, f_o \, t \, ] \, cos[ \, \Phi_{out}(t) \, - \, 2 \, sin[\, 2 \, \pi \, f_n \, t \, ] \, sin[\, \Phi_{out}(t) \, ]\end{displaymath}$

If the phase noise is small, $cos [ \Phi_{out} (t) ] \, \rightarrow \, 1$ and $sin [ \Phi_{out} (t) ] \, \rightarrow \, \Phi_{out} (t)$

then it may be stated:

$\begin{displaymath}\text{out}(t) \; = \; 2 \, cos[ \, 2 \, \pi \, f_o \, t \, ] \, - \, sin[\, 2 \, \pi \, f_n \, t \, ] \, \Phi_{out}(t)\end{displaymath}$

After taking the Fourier Transform, it may be noted that the phase noise consists of two components: the spurious noise is periodic and phase noise is aperiodic.

The phase spectrum can be approximated as:

$\begin{displaymath}S_{\Phi ,out}(f) \; = \; \left(\frac{\, K_v \, }{f} \right)^2 \,S_{vn}(f)\end{displaymath}$

Frequency Resolution

The PLL structure has a period of T where 1/T is the input frequency. In order to average the phase information, the loop filter must have a bandwidth much less than the fundamental frequency – often a factor of 1/10 is used in the initial design stage.

The frequency resolution is defined (and restricted) by the input frequency. It is often desired to increase the resolution without changing the input frequency.